The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having enhance ability of a test for finding fault of a semiconductor memory device.
A semiconductor memory device includes a plurality of memory cells. If any cell in the semiconductor memory device is operated out of order, the semiconductor memory device is useless. After the semiconductor memory device is fabricated, there is needed a test process for finding a defective cell in the semiconductor memory device.
Typically, the semiconductor memory device has an additional area for a test circuit which can test all cells in the semiconductor memory device on high speed. However, according to increasing integration of the semiconductor memory device, there is needed a lot of time and effort for testing cells of the semiconductor memory device so as to research and develop the semiconductor memory device.
FIG. 1 is a block diagram showing a conventional semiconductor memory device.
As shown, the memory device includes four banks 100, 200, 300 and 400. Outputs of the four banks are inputted to a data output buffer 500. The data output buffer 500 outputs a data inputted from the data output buffer 500 into an external circuit through an output pad 500xe2x80x2 in response to a clock singal.
One bank, e.g., 100, includes first and second cell blocks 110 and 150, each having a plurality of cell arrays and I/O sense amplifiers 130 and 140 for respectively amplifying data outputted from the first and the second cell blocks 110 and 150 to output the amplified data to the data output buffer 500.
The first cell block 110 has cell arrays 111 to 116 having a plurality of cells and bit line sense amplifiers 117 to 120 for amplifying and outputting data of cells. Also, the structures of the second to the forth banks 200, 300, and 400 are the same to that of the first banks 100, though the second to the forth banks 200, 300, and 400 are not shown in the FIG. 1 in detail for the sake of convenience.
FIG. 2 describes a preferred embodiment of a bit line sense amplifier logic shown in FIG. 1.
As shown, the bit line sense amplifier 117 includes a bit line sense amplifier 117d for sensing and amplifying a gap between voltages of the bit line pair BL and /BL; an equalization logic 117c for precharging and equalizing the voltage of the bit line pair BL and /BL; a first connection logic 117a for connecting the cell array 111 to one side of the bit line sense amplifier; a second connection logic 117b for connecting the cell array 113 to the other side of the bit line sense amplifier; and an output logic 117e for outputting the bit line voltage amplified by the bit line sense amplifier 117d. Herein, RTO and /S are enable signals which can enable or disable the bit line sense amplifier 117d. BISH and BISL are enable signals which can enable or disable the first and the second connection logic 117a and 117b. Vblp is a bit line voltage which will be precharged. BIEQ is an enable signal which can enable or disable the equalization logic 117c. A column selecting signal YI is an enable signal which can enable or disable the output logic 117e. 
Hereinafter, referring to FIG. 1 and FIG. 2, the data path in the semiconductor memory device is described in detail.
First, if an address is inputted to the memory device, a word line of a selected cell array in a bank is enabled corresponding to the address. A MOS transistor M1 connected to the enabled word line WL is turned on so that data stored in a capacitor C1 is supplied to a bit line pair BL and /BL. Then, the bit line sense amplifier 117d senses and amplifies the data signal because the data signal stored in the capacitor C1 is too weak.
If the column selecting signal YI is enabled, the data signal sensed and amplified by the bit line sense amplifier 117d is outputted to a data line pair DB and /DB. The data outputted data of the data line pair DB and /DB is amplified one more time by a DB sense amplifier, e.g., block 130 shown in FIG. 1, and, then outputted to the external circuit through the output buffer 500.
The DB sense amplifier should be needed for amplifying the weaken data because the data line pair DB and /DB is relatively long. Also, a number of the DB sense amplifier is determined by a size of data simultaneously outputted by the column selecting signal YI. Typically, there is one DB sense amplifier on the front of one bank.
Referring to FIG. 2 that one bit data is outputted to the data line pair DB and /DB by the column selecting signal YI. However, there is recently needed a memory device which can be operated on high speed. Thus, the memory device is designed so that four-bit data is outputted at once to the DB sense amplifier in response to one column selecting signal YI.
The inputted address may be split into a row address and a column address. The row address enables the word line and the column selecting signal YI is generated from the column address.
FIG. 3 is a block diagram showing a conventional test block for testing a synchronous memory device. As shown, one bank, e.g., the first bank 100, includes the first cell block 110 and the second cell block 150. For operation on high speed, the bank has the first and the second cell blocks 110 and 150, and each cell block has a DB sense amplifier and a decoder.
The test block for testing the memory device includes a Y counter 720 for receiving an address AD less than 0 greater than  to AD less than 9 greater than  from the external circuit and orderly counting it; a first and a second YI decoders 740 and 750 for decoding outputted addresses YA less than 0 greater than  to YA less than 9 greater than  from the Y counter and outputting the column selecting signal YI to each of the first and the second cell blocks 110 and 150; DB sense amplifiers 130 and 140 for amplifying an outputted data signal from the first and the second cell blocks 110 and 150; a test circuit 600 for combining an outputted data signal from the DB sense amplifiers 130 and 140 and performing a test process; and an output buffer 530 for buffering an output signal from the test circuit 600 and outputting it to the external circuit through a pad. Furthermore, the bank has an instruction controller for controlling the Y counter 720 by receiving several instruction signals such as /CS, /CAS, and so on.
FIG. 4 is a timing chart showing a test operation of the test block shown in FIG. 3.
Hereinafter, referring to FIG. 3 to 4, the test operation of the memory device is described in detail.
If the several instruction signals inputted to the instruction controller 710 are correspondent to a test mode, the memory device is operated in the test mode. The Y counter 720 receives column addresses AD less than 0 greater than  to AD less than 9 greater than  and counts the column addresses AD less than 0 greater than  to AD less than 9 greater than  by a burst length BL and, outputs the counted column address YA less than 0 greater than  to YA less than 9 greater than . The burst length BL is a kind of specifications in the synchronous memory device; and, in detail, means a number of data which is continuously outputted when one address is inputted. For instance, if the burst length is four, the counter 720 counts the received column addresses at four times and, then outputs the counted column address.
The first YI decoder 740 receives the counted addresses YA less than 0 greater than  to YA less than 9 greater than  outputted from the Y counter 720 and outputs a 8-bit test data by selecting the two YI lines YI less than a greater than  and YI less than b greater than  in YI lines YI less than 0 greater than  to YI less than 1023 greater than . As shown in FIG. 2, a data signal which is sensed by the bit line sense amplifier is outputted by a YI line. It is assumed that four bit data is outputted if one YI line is selected.
If the memory device is operated in a 0xc3x9716 mode, a four-bit data signal is simultaneously outputted by one YI line. If each two YI lines in the first and second cell blocks 110 and 150, i.e., total four YI lines, are selected, a 16-bit data is outputted to external circuit. Herein, it is assumed that the test data is stored in all cells and is directly outputted through the bit line if the YI line is selected by enabling the word line at a predetermined timing.
The second YI decoder 750 also receives the counted addresses YA less than 0 greater than  to YA less than 9 greater than  outputted from the Y counter 720 and outputs a 8-bit test data by selecting the two YI lines YI less than c greater than  and YI less than d greater than  in the YI lines YI less than 0 greater than  to YI less than 1023 greater than . The outputted signals from the first and second YI decoders 740 and 750 are simultaneously outputted and, as a result, each YI line included in each cell block 110 and 150 is simultaneously selected.
The 8-bit test data outputted from the first cell block 110 is sensed and amplified by the first DB sense amplifier 130, and each bit of the 8-bit test data is inputted to each of a first to a forth NOR gates 601 to 604 in the test circuit 600. The 8-bit test data outputted from the second cell block 150 is also sensed and amplified by the second DB sense amplifier 140 and individually inputted to each of the first to the forth NOR gates 601 to 604 in the test circuit 600.
Herein, there is a pattern of the test data group. Each data outputted from a group of the DB sense amplifier is exactly same and each group includes four DB sense amplifiers: for example, first group has the 1st, 5th, 9th and 13th DB sense amplifiers; second group has the 2nd, 6th, 10th and 14th DB sense amplifiers; third group has the 3rd, 7th, 11th and 15th DB sense amplifiers; and fourth group has the 4th, 8th, 12th and 16th DB sense amplifiers.
If the data being same to the initial stored test data is outputted from the first to the sixteenth DB sense amplifiers, output signals of the first to forth NOR gates 601 to 604 are in logical high and, as a result, outputs of the first and second NAND gates 605 and 606 is in logical low. Thus, output of the last NOR gate 607 is in logical high and a signal passing through the output buffer 530 is outputted in logical high to the output pad 530xe2x80x2.
A signal outputted to the output pad 530xe2x80x2 is only one bit signal, but it is considered as a 16 bit data for testing the memory device because it is generated by combining each bit signals in the test circuit 600. If the output pad 530xe2x80x2 outputs a signal in logical low, there is needed a detailed examination about related cells in the memory device.
As shown in FIG. 4, in a test read mode, each 8 bit signal is outputted to the test circuit 600 by each output signal of the first and the second YI decoders 740 and 750. Then, the test of the output signal which is supplied to the output pad 530xe2x80x2 can be considered as examination of 16 cells in memory device. The test process is independently performed at each bank because each bank has one output pad.
In one clock time, 16 cells can be tested by the above manner. So, in the memory device which includes several banks having 4 k cells, it takes 256 clock times to test the total cells of the memory device. Today, typical memory device, e.g., a 512 Mb memory, includes four banks and each bank has 128 Mb cells. Thus, there is needed 8 Mb clock times for testing the total cells in the memory device. There is needed a test block for testing total cells of the memory device faster because the 8 Mb clock times are relatively long time.
FIG. 5 is a schematic circuit diagram showing a part of a Y counter shown in FIG. 3.
The Y counter can includes a plurality of the partial circuits shown in FIG. 5 in response to several inputted addresses. If an address AD less than 0 greater than  is inputted to the Y counter, the Y counter outputs a YA less than 0 greater than  through xe2x80x98Axe2x80x99 path shown in FIG. 5. In a next time, the Y counter outputs the YA less than 0 greater than  through xe2x80x98Bxe2x80x99 path after latching the address AD less than 0 greater than . This operation is controlled by control signals casp and Icasp which are outputted from an instruction controller 710.
For operating a memory device on higher speed, there is developed a double data rate memory device (hereinafter, referred as DDR memory device) which can output a data signal at both a rising and a falling edges of the clock. Furthermore, there has been developed a combo memory device which can be operated like either a single synchronous memory device of the prior art or a DDR memory device according to system circumstance.
FIG. 6 is a block diagram showing another convention of test block for testing a synchronous combo type memory device.
As shown, structure of the test block is similar to that of the test block shown in FIG. 3. However, there are two test circuits 600 and 600xe2x80x2 and each of a first and a second cell blocks 110xe2x80x2 and 150xe2x80x2 has 16 DB sense amplifiers. The test block further includes a path selecting circuit 620 for selectively outputting a data outputted from the test circuits 600 and 600xe2x80x2 to an output buffer 530.
FIG. 7 is a timing chart showing a test operation of the test block shown in FIG. 6 when the synchronous combo type memory device operates in a single mode. The single mode means an operation mode that a data is outputted at a rising edge of a clock signal like a conventional synchronous memory device.
Hereinafter, referring to FIGS. 6 and 7, there is a method for testing the test block in detail when the combo type memory device is operated in the single mode.
Operation of the test block is similar to that of the test block shown in FIG. 3. The first YI decoder 740 receives and decodes address signals YA less than 0 greater than  to YA less than 9 greater than  outputted from the Y counter 720 and, then selects a YI line. The memory device includes 16 DB sense amplifiers in each cell block 110xe2x80x2 and 150xe2x80x2. So, a 16-bit test data is outputted at once to the first test circuit 600 through the DB sense amplifiers by selecting four YI lines.
In addition, the second YI decoder 750 receives and decodes address signals YA less than 0 greater than  to YA less than 9 greater than  outputted from the Y counter 720 and, then selects a YI line. The memory device includes 16 DB sense amplifiers in each cell block 110xe2x80x2 and 150xe2x80x2. So, a 16-bit test data is outputted at once to the second test circuit 600xe2x80x2 through the DB sense amplifiers by selecting four YI lines.
Herein, like the above statement, each data outputted from a group of the DB sense amplifier is exactly same and each group includes four DB sense amplifiers: first group has the 1st, 5th, 9th and 13th DB sense amplifiers; second group has the 2nd, 6th, 10th and 14th DB sense amplifiers; third group has the 3rd, 7th, 11th and 15th DB sense amplifiers; and fourth group has the 4th, 8th, 12th and 16th DB sense amplifiers.
It is assumed that the data stored in the total cells of the cell blocks 110xe2x80x2 and 150xe2x80x2 are initially in logical low. If the data which is initially stored in the memory device are outputted to the 1st to the 16th DB sense amplifiers, output signals of the first to the forth NOR gates 601 to 604 in the first test circuit 600 are in logical high. However, if there is any defective cell in the memory device, the first to the forth NOR gates 601 to 604 cannot output a logic high signal. If there is not any defective cell, output signals of the first and second NAND gates 605 and 606 are in logical low and an output signal of the final NOR gate 607 is in logical high. The output signal from the first test circuit 600 is outputted to an external circuit after passing through the path selecting circuit 620 and the output buffer 530.
Herein, there is not described operation of the second test circuit 600xe2x80x2 because it is the same to that of the first test circuit 600.
Though the output signal of the output pad 530xe2x80x2 is just one bit, it can be considered as a result of testing the 16-bit test data. Namely, 16-bit cells are tested at once in one time test by using one the output pad.
In FIG. 7, in a test read mode, each 16-bit signals outputted from the first and the second YI decoders is outputted to the first and the second test circuits 600 and 600xe2x80x2. It is described operation of the test circuit that 16-bit data is combined and outputted to the output pad 530xe2x80x2.
Each bank uses one output pad, so each bank can independently test its cells in the above manner.
The 16-bit cells can be tested at once. Thus, total testing time of testing the whole cells in the memory device is 256 clock times if the memory device has 4 k banks as shown in FIG. 7. Today, in a high integrated memory device having 128 MB banks, 8 Mb clock times are needed for testing the whole cells in the memory device.
FIG. 8 is a timing chart showing a test operation of the test block shown in FIG. 6 when the synchronous combo type memory device operates in a DDR mode.
As shown, there is difference that the four YI lines are selected at every rising and falling edges of the clock signal by the first and the second YI decoders 740 and 750. Thus, during every one clock time, 32-bit cells can be tested.
In the DDR mode of the memory device having 4 K banks, as shown in FIG. 7, 128 clock times are needed for testing the whole cells of the memory device because 32-bit cells are tested at once. Today, in a high integrated memory device having 128 MB banks, 4 Mb clock times are needed for testing the whole cells of the memory device.
However, there is needed a test circuit which can test two times cells at once because data is continuously outputted at every rising and falling edges of the clock signal. If there is not the test circuit, the memory device must be operated in the single mode.
In conclusion, as the memory device is more integrated, test time of the memory device is a critical issue for effectively testing the memory device and reducing manufacturing cost. There is needed a memory device which can test its cells during shorter time.
It is, therefore, an object of the present invention to provide a synchronous memory device for reducing testing time.
In accordance with an aspect of the present invention, there is provided the memory device which includes at least one bank having first and second unit blocks, each containing a plurality of cell arrays and first and second decoding units for decoding an inputted column address and outputting column selecting signals of the first and second unit blocks, including a column address transmitting unit for simultaneously enabling the first and second decoding unit, regardless of a bit select block signal, which selects the first or second unit blocks, of the inputted column address during a test mode; a first combining circuit for combining test data outputted by the column selecting signal of the first unit blocks and detecting an error of the test data in the test mode; a second combining circuit for combining test data outputted by the column selecting signal of the second unit blocks and detecting an error of the test data in the test mode; and a first and a second output pads for individually outputting each of outputted signals from the first and second combining circuits.